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? semiconductor components industries, llc, 2000 august, 2000 rev. 4 1 publication order number: mc14526b/d mc14526b presettable 4-bit down counters the mc14526b binary counter is constructed with mos pchannel and nchannel enhancement mode devices in a monolithic structure. this device is presettable, cascadable, synchronous down counter with a decoded a0o state output for dividebyn applications. in single stage applications the a0o output is applied to the preset enable input. the cascade feedback input allows cascade dividebyn operation with no additional gates required. the inhibit input allows disabling of the pulse counting function. inhibit may also be used as a negative edge clock. this complementary mos counter can be used in frequency synthesizers, phaselocked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity. ? supply voltage range = 3.0 vdc to 18 vdc ? logic edgeclocked design e incremented on positive transition of clock or negative transition of inhibit ? asynchronous preset enable ? capable of driving two lowpower ttl loads or one lowpower schottky ttl load over the rated temperature range maximum ratings (voltages referenced to v ss ) (note 2.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 3.) 500 mw t a operating temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 2. maximum ratings are those values beyond which damage to the device may occur. 3. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14526bcp pdip16 2000/box mc14526bdw soic16 47/rail marking diagrams 1 16 pdip16 p suffix case 648 mc14526bcp awlyyww mc14526bdwr2 soic16 1000/tape & reel soic16 dw suffix case 751g 1 16 14526b awlyyww 1. for ordering information on the eiaj version of the soic packages, please contact your local on semiconductor representative. soeiaj16 f suffix case 966 1 16 mc14526b alyw mc14526bf soeiaj16 see note 1.
mc14526b http://onsemi.com 2 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 0" cf p2 q2 v dd q1 reset p1 inhibit pe p3 q3 v ss clock p0 pin assignment function table inputs output clock reset inhibit preset enable cascade feedback a0o resulting function x h x l l l asynchronous reset* x x x h h h x x x l h x l l h l h h asynchronous reset asynchronous reset ah x h x x h h y asynchronous reset x l x h x l asynchronous preset l h l x l decrement inhibited l l l x l ec e e b ed decrement inhibited l l l l l no chan g e** (inactive ed g e) h l l l l l l l l l no change (inactive edge) no change** (inactive edge) h l l l l l l l l l no change (inactive edge) decrement** h l l l l l l l l l decrement decrement** x = don't care notes: * * output a0o is low when reset goes high only it pe and cf are low. ** output a0o is high when reset is low, only if cf is high and count is 0000.
mc14526b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) v dd 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (4.) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 e e e 0.05 0.05 0.05 e e e 0 0 0 0.05 0.05 0.05 e e e 0.05 0.05 0.05 vdc a1o level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 e e e 4.95 9.95 14.95 5.0 10 15 e e e 4.95 9.95 14.95 e e e vdc input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 e e e 1.5 3.0 4.0 e e e 2.25 4.50 6.75 1.5 3.0 4.0 e e e 1.5 3.0 4.0 vdc a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 e e e 3.5 7.0 11 2.75 5.50 8.25 e e e 3.5 7.0 11 e e e vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 3.0 0.64 1.6 4.2 e e e e 2.4 0.51 1.3 3.4 4.2 0.88 2.25 8.8 e e e e 1.7 0.36 0.9 2.4 e e e e madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 e e e 0.51 1.3 3.4 0.88 2.25 8.8 e e e 0.36 0.9 2.4 e e e madc input current i in 15 e 0.1 e 0.00001 0.1 e 1.0 m adc input capacitance (v in = 0) c in e e e e 5.0 7.5 e e pf quiescent current (per package) i dd 5.0 10 15 e e e 5.0 10 20 e e e 0.005 0.010 0.015 5.0 10 20 e e e 150 300 600 m adc total supply current (5.) (6.) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (1.7 m a/khz) f + i dd i t = (3.4 m a/khz) f + i dd i t = (5.1 m a/khz) f + i dd m adc 4. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 5. the formulas given are for the typical characteristics only at 25 c. 6. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l 50) vfk where: i t is in m a (per package), c l in pf, v = (v dd v ss ) in volts, f in khz is input frequency, and k = 0.001.
mc14526b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (7.) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ (8.) max unit output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl (figures 4, 5) 5.0 10 15 e e e 100 50 40 200 100 80 ns propagation delay time (inhibit used as negative edge clock) clock or inhibit to q t plh , t phl = (1.7 ns/pf) c l + 465 ns t plh , t phl = (0.66 ns/pf) c l + 197 ns t plh , t phl = (0.5 ns/pf) c l + 135 ns t plh , t phl (figures 4, 5, 6) 5.0 10 15 e e e 550 225 160 1100 450 320 ns clock or inhibit to a0o t plh , t phl = (1.7 ns/pf) c l + 155 ns t plh , t phl = (0.66 ns/pf) c l + 87 ns t plh , t phl = (0.5 ns/pf) c l + 65 ns 5.0 10 15 e e e 240 130 100 480 260 200 propagation delay time pn to q t plh , t phl (figures 4, 7) 5.0 10 15 e e e 260 120 100 520 240 200 ns propagation delay time reset to q t phl (figure 8) 5.0 10 15 e e e 250 110 80 500 220 160 ns propagation delay time preset enable to a0o t phl , t plh (figures 4, 9) 5.0 10 15 e e e 220 100 80 440 200 160 ns clock or inhibit pulse width t w (figures 5, 6) 5.0 10 15 250 100 80 125 50 40 e e e ns clock pulse frequency (with pe = low) f max (figures 4, 5, 6) 5.0 10 15 e e e 2.0 5.0 6.6 1.5 3.0 4.0 mhz clock or inhibit rise and fall time t r , t f (figures 5, 6) 5.0 10 15 e e e e e e 15 5 4 m s setup time pn to preset enable t su (figure 10) 5.0 10 15 90 50 40 40 15 10 e e e ns hold time preset enable to pn t h (figure 10) 5.0 10 15 30 30 30 15 5 0 e e e ns preset enable pulse width t w (figure 10) 5.0 10 15 250 100 80 125 50 40 e e e ns reset pulse width t w (figure 8) 5.0 10 15 350 250 200 175 125 100 e e e ns reset removal time t rem (figure 8) 5.0 10 15 10 20 30 110 30 20 e e e ns 7. the formulas given are for the typical characteristics only at 25 c. 8. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance.
mc14526b http://onsemi.com 5 figure 1. typical output source characteristics test circuit figure 2. typical output sink characteristics test circuit cf pe p0 p1 p2 p3 reset inhibit clock q0 q1 q2 q3 0" v ss v dd = -v gs v oh i oh external power supply cf pe p0 p1 p2 p3 reset inhibit clock q0 q1 q2 q3 0" v ss v dd = v gs v ol i ol external power supply figure 3. power dissipation figure 4. test circuit cf pe p0 p1 p2 p3 reset inhibit clock q0 q1 q2 q3 0" v ss v dd c l c l c l c l c l pulse generator 20 ns 20 ns clock 90% 10% 50% variable width 50% duty cycle v ss v dd device under test test point q or 0" c l * * includes all probe and jig capacitance.
mc14526b http://onsemi.com 6 switching waveforms figure 5. figure 6. v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss t r t f t r t f t f t r t r t f v dd clock any p any q any q clock reset t plh t phl t plh t phl t phl t plh preset enable preset enable any p gnd t w t w t w t w any q or 0" any q or 0" t tlh t thl 1/f max 1/f max 90% 50% 10% 90% 50% 10% 90% 50% 10% 90% 50% 10% 90% 50% 10% 50% 0" 50% 90% 50% 10% t tlh t thl inhibit t plh t phl t phl 50% 50% 50% t su t h 50% 50% valid figure 7. figure 8. figure 9. figure 10. t rem
mc14526b http://onsemi.com 7 pin descriptions preset enable (pin 3) e if reset is low, a high level on the preset enable input asynchronously loads the counter with the programmed values on p0, p1, p2, and p3. inhibit (pin 4) e a high level on the inhibit input pre vents the clock from decrementing the counter. with clock (pin 6) held high, inhibit may be used as a negative edge clock input. clock (pin 6) e the counter decrements by one for each rising edge of clock. see the function table for level requirements on the other inputs. reset (pin 10) e a high level on reset asynchronously forces q0, q1, q2, and q3 low and, if cascade feedback is high, causes the a0o output to go high. a0o (pin 12) e the a0o (zero) output issues a pulse one clock period wide when the counter reaches terminal count (q0 = q1 = q2 = q3 = low) if cascade feedback is high and preset enable is low. when presetting the counter to a value other than all zeroes, the a0o output is valid after the rising edge of preset enable (when cascade feedback is high). see the function table. cascade feedback (pin 13) e if the cascade feedback input is high, a high level is generated at the a0o output when the count is all zeroes. if cascade feedback is low, the a0o output depends on the preset enable input level. see the function table. p0, p1, p2, p3 (pins 5, 11, 14, 2) e these are the preset data inputs. p0 is the lsb. q0, q1, q2, q3 (pins 7, 9, 15, 1) e these are the synchronous counter outputs. q0 is the lsb. v ss (pin 8) e the most negative power supply potential. this pin is usually ground. v dd (pin 16) e the most positive power supply potential. v dd may range from 3 to 18 v with respect to v ss . state diagram mc14526b 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5
mc14526b http://onsemi.com 8 mc14526b logic diagram (binary down counter) cf pe inhibit clock reset 13 3 4 6 10 p0 q0 p1 q1 p2 q2 p3 q3 5711 9 14 15 2 1 12 0" d c t r q pe q d c t r q pe q d c t r q pe q d c t r pe q v dd v dd
mc14526b http://onsemi.com 9 applications information dividebyn, single stage figure 11 shows a single stage dividebyn application. to initialize counting a number, n is set on the parallel inputs (p0, p1, p2, and p3) and reset is taken high asynchronously. a zero is forced into the master and slave of each bit and, at the same time, the a0o output goes high. because preset enable is tied to the a0o output, preset is enabled. reset must be released while the clock is high so the slaves of each bit may receive n before the clock goes low. when the clock goes low and reset is low, the a0o output goes low (if p0 through p3 are unequal to zero). the counter downcounts with each rising edge of the clock. when the counter reaches the zero state, an output pulse occurs on a0o which presets n. the propagation delays from the clock's rising and falling edges to the a0o output's rising and falling edges are about equal, making the a0o output pulse approximately equal to that of the clock pulse. the inhibit pin may be used to stop pulse counting. when this pin is taken high, decrementing is inhibited. cascaded, presettable dividebyn figure 12 shows a three stage cascade application. t aking reset high loads n. only the first stage's reset pin (least significant counter) must be taken high to cause the preset for all stages, but all pins could be tied together, as shown. when the first stage's reset pin goes high, the a0o output is latched in a high state. reset must be released while clock is high and time allowed for preset enable to load n into all stages before clock goes low. when preset enable is high and clock is low, time must be allowed for the zero digits to propagate a cascade feedback to the first nonzero stage. worst case is from the most significant bit (m.s.b.) to the l.s.b., when the l.s.b. is equal to one (i.e. n = 1). after n is loaded, each stage counts down to zero with each rising edge of clock. when any stage reaches zero and the leading stages (more significant bits) are zero, the a0o output goes high and feeds back to the preceding stage. when all stages are zero, the preset enable automatically loads n while the clock is high and the cycle is renewed. figure 11. n counter p0 p1 p2 p3 cf reset inhibit clock pe q0 q1 q2 q3 0" n v dd v ss f in buffer f in n figure 12. 3 stages cascaded n0 n1 n2 n3 n4 n5 n6 n7 p0 p1 p2 p3 q0 q1 q2 q3 f in clock inhibit v ss v dd load n v ss reset 0" pe cf 10 k w v ss p0 p1 p2 p3 q0 q1 q2 q3 clock inhibit reset 0" pe cf clock inhibit reset 0" pe cf p0 p1 p2 p3 q0 q1 q2 q3 n8 n9 n10 n11 v ss v dd buffer lsb msb f in n
mc14526b http://onsemi.com 10 package dimensions pdip16 p suffix plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 soic16 dw suffix plastic soic package case 751g03 issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7
mc14526b http://onsemi.com 11 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z soeiaj16 f suffix plastic eiaj soic package case 96601 issue o
mc14526b http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14526b/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk

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